Organizer:
Chip, International Integrated Circuit Innovation Expo (IICIE)
The global semiconductor industry is undergoing profound restructuring and technological innovation. Chips form the backbone of information technology, supporting strategic industries including AI, new energy vehicles and industrial internet. Nevertheless, China’s chip design sector faces major hurdles: gaps in high-end chip technology, reliance on imported IP and EDA tools, fragmented industrial chains and low conversion rates of research achievements.
Under such circumstances, the journal Chip hosts the Chip Design Forum. This platform brings together industry participants to discuss core technological breakthroughs, industrial coordination and talent training. It facilitates technical innovation and industrial integration, boosting high-quality development of China’s chip industry.
| Time | Topics | Speakers |
|---|---|---|
| 10:00-10:10 | Opening Remarks by Prof. Jiliang Zhang, Forum Chair, Nanjing University of Posts and Telecommunications | |
| 10:10-10:35 | Breaking AI Interconnection Barriers via Optoelectronic Integration | Jiang Xu, Head of Microelectronics Thrust, HKUST(GZ), Director, Guangzhou Key Laboratory of EDA. |
| 10:35-11:00 | High-Reliability Chip EDA Simulation & Verification Platform | Zhipeng Liu, Chairman, Shanghai Xinsiwei Information Tech. Co., Ltd. |
| 11:00-11:25 | Research on Key Technologies of Readout IC for Capacitive MEMS Accelerometer | Jianming Xu, Professor & Vice Dean, School of Integrated Circuits, Sun Yat-sen University. |
| 11:25-11:50 | Photonic Chip Platform for AI and Quantum Computing | Pan Fu, Head of Ecosystem Development, CHIPX. |
| 12:10-14:00 | Exhibition Visit & Lunch | |
| 14:00-14:25 | Chips Empower, Senses Envision the Future | Hongquan Wang, Senior Analog Circuit Design Engineer, Chengdu Sino Microelectronics Technology Co.,Ltd. |
| 14:25-14:50 | AI-Driven Intelligent Logic Synthesis | Jianwang Zhai, Associate Professor, Beijing University of Posts and Telecommunications. |
| 14:50-15:15 | Agentic FPGA: Verifiable Design with Domain LLM and EDA Co-Design | Jietao Cai, CEO, Chengdu Pengye Jiatu Technology Co., Ltd. |
| 15:15-15:40 | HPU: A Novel Programmable Edge AI Chip Architecture | Panfeng Wang, Technical Director, Jingwei Qili (Beijing) Technology Co., Ltd. |
| 15:40-16:05 | Processing-in-Memory GPGPU Architecture | Mingyu Wang, Associate Professor,Sun Yat-sen University. |
| 16:05-16:30 | Domestic Application Scenarios of PUF Technology | Dandong He, Chairman, Nanjing Pufu Information Tech. Co., Ltd. |
| 16:30-17:30 | Exhibition Visit |