Organizer:
International Integrated Circuit Innovation Expo (IICIE), Sichip
As the scale of large model training and inference continues to expand, AI clusters impose higher requirements on network bandwidth, energy efficiency and system scalability. Traditional electrical interconnections are gradually hitting power consumption and bandwidth bottlenecks, making optoelectronic convergence a critical evolutionary path for next-generation computing infrastructure.
Co-Packaged Optics (CPO) integrates optical engines with switching chips and AI chips within a single package to deliver high-speed, low-power data transmission. Meanwhile, advances in chiplets, glass substrates, advanced bonding, 2.5D/3D packaging and collaborative EDA design technologies are driving optoelectronic heterogeneous integration from discrete component innovation toward system-level innovation.
Against the backdrop of the evolution of AI computing infrastructure, this forum centers on the industrialization practices of CPO. It brings together enterprises covering design, manufacturing, packaging, materials, equipment, EDA and end-user applications to jointly discuss new technical routes and industrial ecosystems in the era of optoelectronic convergence.
1.CPO Industry Trends and Diversified Technical Routes: CPO market size forecast for 2026–2028; comparison and integrated evolution of NPO/CPO/XPO technical routes; standardization progress (OIF/UCIe) and industrial ecosystem layout.
2.Breakthroughs in Core Heterogeneous Integration Processes: Mass production optimization of TGV (Through Glass Via) technology; 2.5D/3D stacking and Chiplet co-design; hybrid bonding, low-temperature bonding and micro-bump interconnection technologies; high-reliability thermal management and stress control.
3.Full-process Toolchain and Design Innovation for CPO: End-to-end EDA design, simulation and verification for 1.6T/3.2T CPO; integrated design and tape-out practices of silicon photonic PICs; optoelectronic co-simulation and signal integrity optimization; localization roadmap of domestic EDA tools.
4.Core Technologies of Silicon Photonics and Optical Engines: Mass production of 200G/400G high-speed silicon photonic chips; high-power CW light source and EML laser technologies; high-speed photodetectors and modulators; yield improvement of optical engine coupling and packaging.
5.Mass Production and Testing of CPO: Yield control for large-scale CPO packaging; precision manufacturing and assembly processes; high-speed testing schemes and domestic testing equipment; failure analysis and reliability guarantee.
6.CPO Implementation Practices in AI Data Centers:Application of 1600GbE CPO in ten-thousand-card GPU clusters; integrated liquid cooling and CPO solutions; all-optical interconnection
architecture for large AI factories; cost optimization and commercial feasibility analysis.
7.Collaboration & Opportunities of Domestic CPO Industrial Chain: Breakthroughs in independent and controllable core technologies; upstream-downstream collaboration models;
investment hotspots and startup opportunities; policy support and construction of industrial ecosystem.