As Moore's Law slows, the exponential growth of AI computing needs is spurring the semiconductor industry toward "More than Moore" system-level innovation. This forum focuses on key packaging technology breakthroughs and innovation paths for High-Performance Computing (HPC).

It will delve into 3.5D heterogeneous integration, integrating Hybrid Bonding and 2.5D interposers, while addressing thermal dissipation bottlenecks of high-performance chips. Additionally, it explores the synergistic value of Silicon Photonics Co-Packaged Optics (CPO), Glass Core substrates and optical interconnection in reducing data center latency and optimizing energy efficiency.

Centering on the upgrade from Wafer-level to Panel-level (FOPLP) packaging, the forum gathers industry chain players (equipment, materials, packaging & testing) to analyze CoWoS-to-CoPoS evolution, core equipment pain points and supply chain strategies, outlining a feasible roadmap for large-scale mass production of AI infrastructure packaging technologies.